Nikolaos Malamas

Electrical & Computer Engineer

About

I'm an early-career Electrical & Computer Engineer with a strong interest in computer architecture, FPGA-based systems, high-performance computing and parallel computing. During my studies at the ECE school of TUC, I discovered my passion for designing efficient computing systems and exploring the intersection of hardware and software to tackle challenging computational problems.

My thesis work involved profiling and optimizing an MPI-parallelized Lattice-Boltzmann two-phase flow simulator on the ARIS supercomputer, achieving a maximum parallel speedup of 481.1× on 256 cores with superlinear scaling.

My thesis code was used for production runs, the results of which were used in the work "A Lattice-Boltzmann PI controller approach for constant flux immiscible two-phase flows in porous media" presented at the CMWR conference of 2026. Moreover, my thesis work in the PESXM conference of 2026, under the title "Parallel Speedup Optimization of a Lattice-Boltzmann MPI Program for Applications on Porous Media flows", won me the best presentation award.

Education

Integrated Master's Degree in Electrical and Computer Engineering 2020 – 2026
Technical University of Crete  |  GPA: 7.92/10

Thesis: "Profiling and Parallel Performance Optimization of a Lattice-Boltzmann 2-phase Flow Simulator"  |  Grade: 10/10

  • Identified performance hotspots using Scalasca and Score-P.
  • Optimized MPI parallelism and scalability on the ARIS supercomputer (GRNET), incorporating OpenMP threading.
  • Achieved a maximum parallel speedup of 481.1× on 256 cores, exhibiting superlinear scaling.

Research & Publications

"A Lattice-Boltzmann PI controller approach for constant flux immiscible two-phase flows in porous media" 2026
Contributing Author  |  CMWR Conference 2026
  • Executed production runs on the ATLAS supercomputer using the thesis-developed code.
  • Performed data analysis and processed simulation results for the publication.

Projects

MIPS-like Multi-cycle Pipelining Processor with Data-hazard Handling
Computer Organization course  |  VHDL, Xilinx Vivado
  • Designed and implemented a multi-cycle pipelined processor in VHDL.
  • Developed and tested the design using Xilinx Vivado.
Extension of a Simple OS – TinyOS-3
Operating Systems course  |  C11, Ubuntu Linux
  • Transformed TinyOS-3 processes into multi-threaded ones and implemented a task scheduler based on the Multilevel Feedback Queues algorithm.
  • Implemented inter-process communications through pipes and sockets, and a system call for printing info on running processes.

Achievements & Awards

Best Presentation Award June 2026
15th Greek Scientific Conference of Chemical Engineering (PESXM)

"Parallel Speedup Optimization of a Lattice-Boltzmann MPI Program for Applications on Porous Media flows"

Honorable Mention – "Thales" National Mathematical Competition 2017, 2018, 2019
Hellenic Mathematical Society

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